In low power electronic applications such as portable cellular phones or laptop computers, an important design goal is to minimize power consumption to increase the electronic device's battery lifetime. Such battery powered devices typically operate in a low power mode when the device is not operational or being utilized by the user to conserve battery power. In portable devices having a PLL based clock generation circuit, the PLL is commonly disabled during the low power mode. When switching from low power mode to an operational mode, the PLL is reenabled to provide a system clock for clocking the portable device.
When reacquiring phase-lock after being reenabled or at startup of the system, the PLL will overshoot the target frequency when initially attempting to acquire the programmed system frequency. If the PLL's targeted output frequency is at the maximum specified frequency of the system's processor, the PLL overshoot will cause memory access failures or execution failures in the processor. To prevent these problems in prior art systems, execution control circuitry is included that delays execution within the system's processor until after the PLL acquires phase-lock.
As will be appreciated, a portable device is consuming battery power at an operational level during this delay without the processor being operational. Therefore, it would be desirable to provide a PLL clock generation system that does not introduce the delay in processor execution without risk of overshoot related failures, thus decreasing the time spent in a full power mode.